Profile • RP Node Processing Logic The RP node utilizes a Field-Programmable Gate Array (FPGA) device which provides the primary processing capability for this node type. FPGAs offer customization of the processing logic allowing the RP node to function for a variety of applications. Reprogrammable FPGAs are preferred over one-time-programmable (OTP) FPGAs...
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Processing Logic
Profile • SMAC Processing Logic The SMAC utilizes a radiation-hardened, non-volatile FPGA device to provide the primary processing capability for SMAC functions. This FPGA shall always be powered on when system power is applied regardless of the power state of the remainder of the node. It is recommended to use local POL...
Protocols
Specification • The protocols described in the following sections are used for various SpaceWire applications depending on the needs of the communication interface. Remote Memory Access Protocol (RMAP) is a SpaceWire standard used for memory access. JAS Efficient Exchange Protocol (JEEP) and JAS Reliable Data Delivery Protocol (JRDDP) are both specific to...
Quasi-Static Loads
Specification • Quasi-static loads shall be applied per the program Strength Qualification Plan. The axial and radial acceleration loads are to be applied simultaneously for an 11 g (TBD?) load in the worst case direction.
Radiation Effects Mitigation
Specification • The primary space effect requiring mitigation is the radiation environment, which causes gradual degradation of electronic devices and single event effects (SEE). Parts that have demonstrated destructive SEE, such as SEL or SEGR, should not be incorporated into the node unless absolutely necessary. It is equally important to test the...
RapidIO Interconnect
Profile • RapidIO technology is a packetized point-to-point interconnect fabric. Packets carry user-definable payloads from 1 to 256 bytes. Both serial and parallel physical interfaces are defined, allowing effective data rates from 667 Mbps to 30 Gbps. The serial version of RapidIO was chosen for JAS because it requires a small number...
RapidIO Logical
Profile • The Logical Layer specifications define the operations and associated transactions by which end point processing elements communicate with each other. It is composed of several specifications, each providing packet formats and protocols for different transaction semantics. The Logical I/O specification defines packet formats for read, write, write-with-response, and various atomic...
RapidIO Physical
Profile • The Physical Layer defines how adjacent processing elements electrically connect to each other. The physical layer specifications describe the electrical requirements for connecting endpoints and switches together. The Parallel Physical specification was deprecated in 10/2013 and is no longer used. The Serial Physical specification outlines the requirement for devices utilizing...
RapidIO Transport
Profile • The Transport Layer defines how transactions are routed from one end point processing element to another through switch processing elements. The Transport specification describes the header information added to a RapidiIO packet and the way the header information is interpreted by a switching fabric. Every RapidIO endpoint is uniquely identified...
Rear Transition Module
Profile • This instantiation provides a breakout for backplane signals per the VITA 46.10 specification. A rear transition module (RTM) attaches to the back side of a backplane directly behind and in-line with a front plug-in module (usually a node). The RTM provides accessibility to signals such as communication breakouts, power connectivity,...
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