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PCI Express

Specification • PCI Express, or PCIe, is another multi-lane high speed serial interconnect technology. Each lane is a full-duplex data stream comprised of two differential signaling pairs, one for transmitting and one for receiving.

Electrical Specification > Communication Data Links > PCI Express

Platform Management Service

Specification • The platform management service, service type address 130 is used to configure, manage, and monitor network specific resources. The currently defined platform management service parameters are shown in the following table. Service Type Service Subtype Subtype Description Cmd Tlm Service Parameters Data Types and Description 130 11 Network Topology Upload...

Communication Specification > JAS Packets > Packet Service Definitions > JAS Specific Services Definitions > Platform Management Service

Potential Flight Capability

Specification • Each component of the JAS mechanical structure should consider Flight capability as this will force consideration of design, flight, and test environments described in this specification. The JAS mechanical structure should be designed for the specific application intended.

Mechanical Specification > Mechanical Interface Design > Potential Flight Capability

Power Conversion

Profile • RP Node Power Conversion The input power for RP nodes is provided by a single voltage rail that is distributed throughout the system. This distributed voltage is typically a higher voltage than those required by the components on the board (typically +5 volts) in order to improve efficiency by minimizing...

Reconfigurable Processing Profile > Functional Description > Power Conversion

Power Distribution Architecture

Specification • JAS will accept at least one primary input power source supplied to the system. The primary input power will connect directly to the Power Supply or PS node in a JAS arrangement. The PS node converts the primary input voltage to a lower voltage which is then sent to all...

Electrical Specification > Power Distribution Architecture

Power Supply Profile

Other • The PS profile defines a high-performance power solution, suitable for powering JAS nodes. The PS profile works alongside other nodes within the JAS architecture. The SMAC and Communications profile implement connectivity and data transfer from PS nodes to other nodes in the system. Power Supply Node The figure below illustrates...

Joint Architecture Standard Overview > JAS Profile Introductions > Power Supply Profile

Pressure

Specification • The JAS structure shall meet all performance specifications during and after exposure to pressures varying from atmospheric to the space environment of 10-14 Torr. All thermal-vacuum ground based testing shall be conducted at pressures less than 10-6 Torr.

Environmental Specification > Pressure

Pressure Change

Specification • The structure shall be designed to survive the change of pressure specified in the figure below. The launch and ascent pressure environment will lie between Pc(Max) and Pc(MIN). Pressure Change Within the envelope defined in figure above, the local rates of change will remain between the values shown in the...

Environmental Specification > Pressure > Pressure Change

Processing Logic

Profile • RP Node Processing Logic The RP node utilizes a Field-Programmable Gate Array (FPGA) device which provides the primary processing capability for this node type. FPGAs offer customization of the processing logic allowing the RP node to function for a variety of applications. Reprogrammable FPGAs are preferred over one-time-programmable (OTP) FPGAs...

Reconfigurable Processing Profile > Functional Description > Processing Logic

Protocols

Specification • The protocols described in the following sections are used for various SpaceWire applications depending on the needs of the communication interface. Remote Memory Access Protocol (RMAP) is a SpaceWire standard used for memory access. JAS Efficient Exchange Protocol (JEEP) and JAS Reliable Data Delivery Protocol (JRDDP) are both specific to...

Communication Specification > SpaceWire > Protocols

Quasi-Static Loads

Specification • Quasi-static loads shall be applied per the program Strength Qualification Plan. The axial and radial acceleration loads are to be applied simultaneously for an 11 g (TBD?) load in the worst case direction.

Environmental Specification > Loads > Quasi-Static Loads

Radiation Effects Mitigation

Specification • The primary space effect requiring mitigation is the radiation environment, which causes gradual degradation of electronic devices and single event effects (SEE). Parts that have demonstrated destructive SEE, such as SEL or SEGR, should not be incorporated into the node unless absolutely necessary. It is equally important to test the...

Environmental Specification > Radiation Effects Mitigation

Rear Transition Module

Specification • The rear transition module (RTM) of the VPX standard is a plug-in module at the back of the circuit card chassis that is in line with the front plug-in module or node. The backplane connectors on the RTM are the same as those used on the plug-in nodes. Also, as...

Electrical Specification > Electrical Interconnects > VPX > Rear Transition Module

Reconfigurable Processing Profile

Other • The Reconfigurable Processing (RP) profile defines a high-performance processing solution suitable for constructing nodes for mission data processing, sensor interfaces, and other applications requiring high-bandwidth processing and communications. Nodes based on the RP profile work alongside other nodes within the JAS architecture. The SMAC Profile and the Communication Profile implement...

Joint Architecture Standard Overview > JAS Profile Introductions > Reconfigurable Processing Profile

Reconfigurable Processing Profile

Profile • The RP profile defines a high-performance processing solution suitable for constructing nodes for mission data processing, sensor interfaces, and other applications requiring high-bandwidth processing and communications. The RP profile works alongside the CH Profile and PS Profile to implement nodes within the JAS architecture. The SMAC Profile and the Communication...

Reconfigurable Processing Profile

RP_Applications

Profile • Common instantiations of the RP profile include, but are not limited to: Sensor interface Mission data processing High-Speed Data switch Volatile Memory Storage Softcore processing

Reconfigurable Processing Profile > RP_Applications

Screened Venting

Specification • Where venting requires a screen to maintain cleanliness requirements, based on a 5µ Pall Rigidmesh screen, there shall be 1.5 in^2 or greater screen area per ft^3 of volume where the volume is the sum of multiple daisy-chained volumes. The daisy chained volumes shall be vented.

Mechanical Specification > Environmental Exposure > Venting > Screened Venting

Secondary POL Conversion

Specification • JAS nodes should include POL conversion as needed. POL conversion has become very popular as the voltage requirements of electronic components have continued to drop. It is quite common for many digital electronic devices to use voltages of 1.8 VDC and below. Routing high current, low voltages around a printed...

Electrical Specification > Power Distribution Architecture > Secondary POL Conversion

Sensor Interface and Mission Data Processing

Profile • The primary role of the RP node in this application is to process mission-specific sensor data. Additionally, the node can also be designed to interface to a variety other sensor types by incorporating instantiations of the Expansion Profile. Sensor Interface and Mission Data Processing Instantiation The RP node can also...

Reconfigurable Processing Profile > RP_Applications > Sensor Interface and Mission Data Processing

Serial RapidIO

Specification • Serial RapidIO (or just RapidIO) is a high-performance packet-switched, interconnect technology utilizing either 8b/10b or 64b/67b encoding on data links, or lanes, with speeds up to 6.25 Gbps. Multiple lanes may be used in increase data throughput.

Electrical Specification > Communication Data Links > Serial RapidIO

Softcore Processor Instantiation

Profile • One powerful application that is frequently utilized on FPGA-based platforms is softcore processing. Softcore processors can be instantiated within the FPGA by configuring the FPGA’s logic elements to implement the microprocessor functionality. The microprocessor can easily be integrated with other logic within the FPGA to form a system-on-chip (SoC) architecture....

Reconfigurable Processing Profile > RP_Applications > Softcore Processor Instantiation

Results 101–125 of 147