Radiation Effects Mitigation

The primary space effect requiring mitigation is the radiation environment, which causes gradual degradation of electronic devices and single event effects (SEE).

Parts that have demonstrated destructive SEE, such as SEL or SEGR, should not be incorporated into the node unless absolutely necessary. It is equally important to test the long-term degradation caused by TID to ensure that the parts incorporated will last for the duration of the mission. Whenever possible, radiation-hardened or radiation-tolerant parts should be utilized.

Non-destructive SEE must also be carefully considered. In particular, SEU and SET effects can cause erroneous operation through changing configurations, software, or stored memory values. The result of these effects also has a significant impact on the reliability of the system and can impact the system just as significantly as destructive SEE. For example, a SEU that turns on the control to a motor may cause a sensor to swing into an obstruction, thus damaging the instrument.

There are three main categories of FPGA technologies used in space, defined by the method in which they store their logic configuration: antifuse, flash, and SRAM. These three categories vary widely in many respects, including power consumption, radiation hardness, performance, and integrated features. Antifuse-based FPGAs have a configuration that is immune to SEU, but these devices can only be configured once and have considerably lower performance than other FPGAs. SRAM-based FPGAs, whose configuration is stored in volatile SRAM bits, offer the highest performance but require reconfiguration at every power-up. Additionally, the SRAM array containing the FPGA configuration has varying susceptibility to SEU depending on the underlying technology. Flash-based FPGAs use flash cells to hold the device configuration and offer a reasonable compromise between antifuse- and SRAM-based FPGAs. However, flash-based FPGAs often have much lower TID due to the construction of the flash cell, and thus should not be considered for long duration missions.

One area where FPGA selection is critical is when following the recommendation where the SMAC logic is implemented in a dedicated FPGA. Since this FPGA is always on, handles critical control elements of the node, and helps form the network backbone for the system, it is important that this FPGA never fail, last the duration of the mission, and be as immune to upsets as possible. Thus, a radiation-hardened FPGA is recommended for the SMAC.

For critical applications that must have minimal downtime or extended lifetimes, additional active and passive mitigation can be implemented to slow or prevent radiation-induced SEE. For example, shielding can slow the rate of dose accumulation and TID effects to extend the lifetime of low-TID-rated parts. Within FPGAs, SEE immunity can be improved by triplicating a design’s logic using a scheme called Triple Module Redundancy (TMR). TMR helps prevent radiation-induced configuration errors from propagating through the FPGA until a specialized configuration memory correction circuit (often referred to as a “scrubber”) can repair the configuration memory upset. When utilizing memories, Error Detection and Correction (often implemented internally in the memory device or through the FPGA logic) can add check bits to a memory word to automatically detect and correct many common patterns of upset bits. It is highly recommended to add some form of mitigation to any radiation-susceptible device, whether it is an FPGA, memory, or other circuitry.

Another area that needs special consideration with respect to radiation performance is the POL converters. Radiation-hardened POL devices are highly recommended. POL converters that are susceptible to radiation may fail by shorting the regulated voltage to the input source, which has a high probability of causing a catastrophic failure to devices connected to that power rail.

Depending on the reliability requirements of the intended mission, it is important to consider both the susceptibility of the electronics incorporated into the node and any necessary mitigation that may also be necessary to ensure proper operation.